10+ years custom digital/analog layout design experience
Proficiency in cadence virtuoso or synopsys custom compiler
Strong understanding of semiconductor fabrication processes
You will drive physical layout implementation of memory building blocks including control circuits, sense amplifiers, and bit cell arrays within a compiler framework
Job Summary
You will drive physical layout implementation of memory building blocks including control circuits, sense amplifiers, and bit cell arrays within a compiler framework.
This senior role requires providing expert engineering judgment for critical decision-making, including IR drop analysis, reliability verification, and project schedule optimization.
The position offers the opportunity to work on cutting-edge memory technologies while leading technical initiatives and developing the next generation of layout engineering talent.
Matching Summary
You will drive physical layout implementation of memory building blocks including control circuits, sense amplifiers, and bit cell arrays within a compiler framework.
Skills & Requirements
Must-have
10+ years custom digital/analog layout design experience
Proficiency in Cadence Virtuoso or Synopsys Custom Compiler
Strong understanding of semiconductor fabrication processes
Experience with DRC/LVS/RV verification and debugging
Basic programming skills in UNIX shell scripting, Tcl, or Perl
Nice-to-have
Layout automation and scripting experience
Advanced Python programming skills
Experience with memory compilers and architectures
Knowledge of FinFET or advanced device technologies
Experience mentoring junior engineers
Key Requirements
Bachelor's degree in Electronic/Microelectronic Engineering or related discipline
Minimum 10 years of layout design experience
Experience with advanced technology nodes (14nm and below) preferred