Director Of Engineering – Asic Design

NXP Semiconductors

Hyderabad, India
Asic front-end design
Soc architecture
Rtl design verilog/systemverilog
Lead front-end design of advanced SoCs, sub-systems optimized for AI inference, networking, and edge compute workloads

Job Summary

  • Lead front-end design of advanced SoCs, sub-systems optimized for AI inference, networking, and edge compute workloads.
  • Build, mentor, and lead high-performing teams across, RTL, and integration, fostering a culture of engineering excellence.
  • Partner closely with physical design teams and support backend sign-off and silicon bring-up, ensuring first-silicon success.

Matching Summary

Lead front-end design of advanced SoCs, sub-systems optimized for AI inference, networking, and edge compute workloads.

Skills & Requirements

Must-have

  • ASIC front-end design
  • SoC architecture
  • RTL design Verilog/SystemVerilog
  • microarchitecture design
  • functional verification
  • performance and power modeling

Nice-to-have

  • system-level thinking
  • people leadership
  • engineering excellence
  • accountability and innovation

Key Requirements

  • 15+ years of experience in ASIC front-end design
  • Proven delivery of complex SoCs / AI accelerators
  • Strong background in architecture, RTL, verification, timing, power, and silicon bring-up
  • Low-power design experience
  • Python, Perl, TCL scripting skills

Work Rights

Not specified

Tailored Resume

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