Proven experience with graph lowering and ir design
This role involves architecting and implementing high-impact compiler subsystems including IR design, lowering pipelines, and target code generation for NPU accelerators
Job Summary
This role involves architecting and implementing high-impact compiler subsystems including IR design, lowering pipelines, and target code generation for NPU accelerators.
The successful candidate will drive low-level optimizations and collaborate with kernel teams to close the hardware-software performance gap while ensuring numerical correctness.
You will mentor senior and junior engineers, enforce best practices for compiler CI, and influence the product roadmap by identifying compiler-driven feature opportunities.
Matching Summary
This role involves architecting and implementing high-impact compiler subsystems including IR design, lowering pipelines, and target code generation for NPU accelerators.
Skills & Requirements
Must-have
Deep expertise in ML compilers and toolchains
Expert C++ and solid Python programming skills
Proven experience with graph lowering and IR design
Strong systems programming and debugging capabilities
Track record of shipping production compiler components
Nice-to-have
Passion for mentorship and improving engineering practices
Experience influencing product and silicon roadmaps
Ability to represent company in technical customer engagements
Collaboration with hardware architects and kernel teams
Key Requirements
Deep expertise in ML compilers (MLIR, LLVM, TVM, XLA)
Expert C++ and solid Python systems programming skills
Demonstrated track record of shipping production compiler components
Excellent debugging and profiling skills with performance toolchains