The role involves logic design of component and foundation IPs which can be used to build an SoC chassis
Job Summary
The role involves logic design of component and foundation IPs which can be used to build an SoC chassis.
The Central Engineering Group (CEG) builds scalable engineering solutions across Product Enablement, Custom ASIC, and Foundry Enablement.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Matching Summary
The role involves logic design of component and foundation IPs which can be used to build an SoC chassis.
Skills & Requirements
Must-have
Verilog/System Verilog skills
high-performance data plane routers
control plane switches
protocol conversion bridges
AMBA/CXL protocols
logic design of IPs
Nice-to-have
understanding of QoS
access control
flow control
debug
RAS
security
error handling
AI to assist logic design
Key Requirements
Bachelor's/Master's degree in Science, Electrical Engineering or equivalent
4+ years of experience in SOC and/or IP design
4+ Experience in Verilog/System Verilog, Lint/CDC/RDC
Familiarity with AMBA and PCIe/CXL protocols
Experience working with architecture, verification SoC integration teams
Good understanding of PPA trade-offs
Ability to work with physical design to solve timing issues