Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing
Job Summary
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Participates in the development and improvement of physical design methodologies and flow automation.
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across multiple pillars to deliver measurable business impact.
Matching Summary
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Skills & Requirements
Must-have
Physical design implementation
ASIC/SOC implementation experience
Synthesis and place and route
Static timing analysis
Power and noise analysis
System Verilog/SOC development environment
Scripting with PERL, TCL, Python
Nice-to-have
Low power/UPF implementation techniques
Formal verification techniques
Knowledge of industry standard protocols
Hardware validation techniques
Physical clock design expertise
Design for test (DFT) using EDA tools
Flow automation and methodology improvement
Key Requirements
BTech/MTech degree
10+ years ASIC/SOC implementation experience
Strong understanding of system and processor architecture
Experience designing complex blocks like CPUs, GPUs, Media blocks, Memory controllers
Experience with scripting languages PERL, TCL, Python