The role involves driving all stages of physical design including floor planning, placement, CTS, routing, and optimization for high-speed digital blocks
Job Summary
The role involves driving all stages of physical design including floor planning, placement, CTS, routing, and optimization for high-speed digital blocks.
Candidates will own timing closure strategies, perform signal/power integrity analysis, and apply OPC litho shrink methodologies at advanced nodes.
This position requires building automation scripts in TCL, Python, or Perl to streamline flows and improve engineering efficiency.
Matching Summary
The role involves driving all stages of physical design including floor planning, placement, CTS, routing, and optimization for high-speed digital blocks.
Skills & Requirements
Must-have
5+ years physical design experience
Advanced node TSMC N4P/N3 implementation
Synopsys ICC2 or Cadence Innovus proficiency
Timing closure and ECO strategies
Signal and power integrity analysis
OPC litho shrink methodologies
TCL Python Perl scripting skills
Nice-to-have
DFT techniques scan insertion ATPG
Multi-patterning LELE SAQP experience
Full signoff verification DRC LVS DFM
Data-driven debugging mindset
Collaboration with cross-functional teams
Key Requirements
5+ years experience in physical design for digital ASICs
Hands-on experience with TSMC N5/N4P/N3 nodes
Proficiency with Synopsys ICC2, Cadence Innovus, Calibre, PrimeTime
Strong scripting capabilities in TCL, Python, or Perl