Senior Asic Design - Cisco Silicon One

Cisco

Caesarea, ,
Rtl design with verilog/systemverilog
Micro-architecture specification writing
Timing and performance optimization
Cisco Silicon One is transforming the industry with a unified, programmable architecture powering Cisco’s future routing portfolio and shaping the Internet for decades to come

Job Summary

  • Cisco Silicon One is transforming the industry with a unified, programmable architecture powering Cisco’s future routing portfolio and shaping the Internet for decades to come.
  • Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
  • We work as a team, collaborating with empathy to make really big things happen on a global scale.

Matching Summary

Cisco Silicon One is transforming the industry with a unified, programmable architecture powering Cisco’s future routing portfolio and shaping the Internet for decades to come.

Skills & Requirements

Must-have

  • RTL design with Verilog/SystemVerilog
  • Micro-architecture specification writing
  • Timing and performance optimization
  • Collaboration with verification engineers
  • Debug and post-silicon validation

Nice-to-have

  • MATLAB simulations experience
  • Mixed-signal systems familiarity
  • Clock Domain Crossing expertise
  • Support design methodology evolution

Key Requirements

  • B.Sc./M.Sc. in Electrical Engineering
  • RTL design experience
  • Familiarity with UVM and functional verification methodologies

Work Rights

Not specified

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