Front End Asic Rtl/logic Senior Design Engineer

Altera

Penang, Malaysia
10 years asic frontend experience
Rtl coding using hdl languages
High speed digital design implementation
The role involves leading the definition and implementation of micro-architecture and RTL for high-speed digital designs in next-generation IO

Job Summary

  • The role involves leading the definition and implementation of micro-architecture and RTL for high-speed digital designs in next-generation IO.
  • Candidates must possess a minimum of 10 years of ASIC frontend experience with strong analytical and problem-solving skills.
  • The position requires close collaboration with verification and back-end teams to ensure successful floor planning and timing closure.

Matching Summary

The role involves leading the definition and implementation of micro-architecture and RTL for high-speed digital designs in next-generation IO.

Skills & Requirements

Must-have

  • 10 years ASIC frontend experience
  • RTL coding using HDL languages
  • High speed digital design implementation
  • Synthesis, STA timing closure, and CDC
  • Post Silicon debug and characterization

Nice-to-have

  • Strong communication and leadership skills
  • Scripting knowledge desirable
  • Experience with multi-GHz designs
  • Collaboration with verification teams

Key Requirements

  • BS/MS or PhD in Electronics Engineering
  • Minimum 10 years of ASIC frontend experience
  • Proficiency with Spyglass, Synthesis, and STA tools

Work Rights

Not specified

Tailored Resume

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