Senior Si/pi Hardware Engineer, Technical Lead (ddr, Pcie) (onsite)

Cisco UK

San Jose, California, United States
Base: $191,400.00 to $281,400.00; bonus/equity: el...
11+ years signal/power integrity experience
High-speed link modeling ddr pcie cxl
3d electromagnetic simulation expertise
This role involves leading the design and analysis of high-speed interconnects and power distribution networks for next-generation compute servers

Job Summary

  • This role involves leading the design and analysis of high-speed interconnects and power distribution networks for next-generation compute servers.
  • The successful candidate will perform pre- and post-route signal integrity analysis using advanced simulations and statistical methods.
  • Cisco offers a competitive salary range, comprehensive benefits including medical and dental insurance, and opportunities for stock unit grants.

Matching Summary

This role involves leading the design and analysis of high-speed interconnects and power distribution networks for next-generation compute servers.

Salary

Base: $191,400.00 to $281,400.00; Bonus/Equity: Eligible for restricted stock units and annual bonuses; Benefits: Medical, dental, vision, 401(k) match, paid time off

Skills & Requirements

Must-have

  • 11+ years Signal/Power Integrity experience
  • High-speed link modeling DDR PCIe CXL
  • 3D electromagnetic simulation expertise
  • PCB stack-up and DFM decision making
  • VNA TDR Scope lab measurement skills

Nice-to-have

  • Experience with ICAT or Seasim tools
  • Knowledge of optical transceiver modules
  • Strong mentorship and leadership abilities
  • Proficiency in MATLAB and HSpice
  • Collaboration across cross-functional teams

Key Requirements

  • Bachelor's degree in EE or Physics plus 11+ years experience
  • Masters in EE or Physics plus 7 years experience
  • PhD in EE or Physics plus 4 years experience
  • Must commute to San Jose CA office 5 days per week

Work Rights

Not specified

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