Asic Link Modeling Technical Leader

Cisco UK

New York City Metro Area, USA
Base: $189,300.00 - $350,800.00; bonus/equity: not...
On-site
High-speed serdes modeling
Optical dsp modeling
Die-to-die interface modeling
Cisco is seeking an experienced ASIC Link Modeling Technical Leader to join their Client Optics Group in the New York City Metro Area. The ideal candidate will have extensive experience in ASIC link modeling, high-speed communication theory, and proficiency in relevant programming languages, contributing to the development of advanced optical technologies

Job Summary

  • Develop system-level behavioral models and comprehensive link simulations for Cisco's silicon photonics systems, enabling performance analysis across high-speed SerDes, optical DSP, and die-to-die interfaces for next-generation 100G/200G/400G per Lambda solutions.
  • Lead link budget analysis, channel modeling, and statistical simulations to evaluate jitter, noise, crosstalk, and bit error rate (BER) across transmit and receive paths.
  • Collaborate across cross-functional teams to develop IBIS-AMI models, create modeling documentation, and support product release from concept through production.

Matching Summary

Match Score: 85

Cisco is seeking an experienced ASIC Link Modeling Technical Leader to join their Client Optics Group in the New York City Metro Area. The ideal candidate will have extensive experience in ASIC link modeling, high-speed communication theory, and proficiency in relevant programming languages, contributing to the development of advanced optical technologies.

Salary

Base: $189,300.00 - $350,800.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k) with match, paid time off

Skills & Requirements

Must-have

  • high-speed SerDes modeling
  • optical DSP modeling
  • die-to-die interface modeling
  • Python, C/C++, MATLAB proficiency
  • EDA and SI simulation tools

Nice-to-have

  • optical DSP experience
  • PAM4 modulation techniques
  • IBIS-AMI model development
  • post-silicon validation

Key Requirements

  • Bachelors + 12 years or Masters + 8 years or PhD + 5 years experience
  • High-speed communication theory
  • Transmission line theory
  • SerDes, Ethernet, D2D PHY protocols
  • DSP fundamentals

Work Rights

Not specified

Tailored Resume

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