Senior Design Verification Engineer - Interconnect Ip
Nvidia Corporation
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System verilog
Python/perl
C/c++ programming
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Nvidia Corporation is seeking a Senior Design Verification Engineer for their FBHUB team in Shanghai, focusing on memory subsystem IP design and verification. The ideal candidate should have over four years of relevant experience and expertise in verification methodologies, programming skills, and a collaborative spirit.
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Job Summary
The FBHUB Shanghai team focuses on memory subsystem IP design and verification, contributing to FBHUB RTL development, verification infrastructure, coverage analysis, and performance validation.
The responsibility includes verification on FBHUB end-to-end functionality, performance and power optimization, etc.
Participate in the research of verification methodology to improve automation and productivity to produce NVIDIA's new high-quality state of the art products.
Matching Summary
Match Score: 75
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Nvidia Corporation is seeking a Senior Design Verification Engineer for their FBHUB team in Shanghai, focusing on memory subsystem IP design and verification. The ideal candidate should have over four years of relevant experience and expertise in verification methodologies, programming skills, and a collaborative spirit.
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Skills & Requirements
Must-have
System Verilog
Python/Perl
C/C++ programming
verification methodology
verification tools and flow
Nice-to-have
AI coding tools
complex TB setup
SVA
functional coverage group
random constraint
English communication skills
Key Requirements
4+ years work experience
Bachelor's (BS) or Master's (MS) degree
Electrical Engineering, Computer Engineering, or related fields