The Senior ASIC Hardware Verification Engineer is responsible for the end-to-end functional verification of complex digital designs (IP, Subsystem, or SoC)
Job Summary
The Senior ASIC Hardware Verification Engineer is responsible for the end-to-end functional verification of complex digital designs (IP, Subsystem, or SoC).
You will architect advanced UVM-based testbenches, define exhaustive verification plans, and lead the "coverage closure" process to ensure the design meets all architectural specifications before tape-out.
Provide technical leadership to junior engineers and perform code reviews for testbench components.
Matching Summary
The Senior ASIC Hardware Verification Engineer is responsible for the end-to-end functional verification of complex digital designs (IP, Subsystem, or SoC).