Jasper Formal Verification - Sr Principal Application Engineer

Cadence

Base: $143,500 to $266,500 (california); bonus/equ...
System verilog rtl design expertise
Formal property-checking tools application
Unix and tcl scripting proficiency
This role involves collaborating with prominent semiconductor companies to implement Cadence's Jasper Formal Verification solutions

Job Summary

  • This role involves collaborating with prominent semiconductor companies to implement Cadence's Jasper Formal Verification solutions.
  • The position requires providing hands-on technical support throughout both pre-sale and post-sale stages while building strong client relationships.
  • Candidates will benefit from a comprehensive benefits package including paid vacation, 401(k) match, and employee stock purchase plans.

Matching Summary

This role involves collaborating with prominent semiconductor companies to implement Cadence's Jasper Formal Verification solutions.

Salary

Base: $143,500 to $266,500 (California); Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, 401(k), medical/dental/vision

Skills & Requirements

Must-have

  • System Verilog RTL design expertise
  • Formal property-checking tools application
  • UNIX and TCL scripting proficiency
  • Simulation-based verification concepts
  • Seven years industry experience

Nice-to-have

  • Mentoring junior team members
  • Representing company at conferences
  • Self-driven independent work style
  • Advanced degree in related field

Key Requirements

  • Minimum seven years of relevant industry experience
  • Advanced degree in a related field highly desirable
  • Deep expertise in formal verification scenarios

Work Rights

Not specified

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