Principal Logic Design Engineer

Altera Digital Health

New Delhi, India
Fully remote
System verilog
Vcs/synopsys simulators
Lint and synthesis
Altera is driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure

Job Summary

  • Altera is driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.
  • Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
  • Involve in IP design example brings up on hardware, hardware verification and failure debugging.

Matching Summary

Altera is driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.

Skills & Requirements

Must-have

  • System Verilog
  • VCS/Synopsys simulators
  • Lint and Synthesis
  • RTL coding and simulation
  • mixed-signal and high-speed IPs

Nice-to-have

  • FPGA design and programming
  • RTL validation experience
  • good communication skills
  • problem-solving skills

Key Requirements

  • 15+ years' experience
  • Bachelor's or Master's degree
  • Electrical Engineering or Computer Engineering
  • C/C++/Perl/Python/TCL/Unix Shell script programming

Work Rights

Not specified

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