Senior Staff Static Timing Analysis & Physical Design Engineer

Marvell

Burlington, VT, US
Base: not specified; bonus/equity: employee stock ...
Onsite
Bachelor's degree in electrical engineering or computer science
5-10 years of professional experience in digital design
Expertise in full-chip and sub-hierarchy integration
Marvell is seeking a Senior Staff Static Timing Analysis & Physical Design Engineer to join their team in Burlington, VT. The role involves performing static timing analysis, collaborating with various engineering teams, and mentoring junior staff, all while contributing to the development of high-performance processors and data center chips

Job Summary

  • This role offers the opportunity to work on timing analysis and methodology for next-generation high-performance processors and data center chips.
  • The team is located in Burlington, VT, and provides relocation assistance for qualified candidates who do not currently reside there.
  • Marvell offers comprehensive benefits including an employee stock purchase plan, family support programs, and robust mental health resources.

Matching Summary

Match Score: 85

Marvell is seeking a Senior Staff Static Timing Analysis & Physical Design Engineer to join their team in Burlington, VT. The role involves performing static timing analysis, collaborating with various engineering teams, and mentoring junior staff, all while contributing to the development of high-performance processors and data center chips.

Salary

Base: Not specified; Bonus/Equity: Employee stock purchase plan available; Benefits: Comprehensive financial well-being, family support, and health resources

Skills & Requirements

Must-have

  • Bachelor's degree in Electrical Engineering or Computer Science
  • 5-10 years of professional experience in digital design
  • Expertise in full-chip and sub-hierarchy integration
  • Strong scripting skills in TCL, Python, and Shell
  • Experience with RTL to GDS flows and methodology

Nice-to-have

  • Experience with PrimeTime static timing analysis tools
  • Knowledge of advanced Clock Tree Synthesis techniques
  • Familiarity with machine-learning-assisted timing methodologies
  • Experience with Tessent DFT based designs
  • Understanding of UPF and low-power design methodologies

Key Requirements

  • Bachelor's degree with 5-10 years experience or Master's/PhD with 3-5 years
  • Eligibility to access export-controlled information under US law
  • Must be a US citizen, lawful permanent resident, or protected individual

Work Rights

Must have US citizenship, lawful permanent resident status, or protected individual status

Tailored Resume

Cover Letter