Senior Design Engineer

Astera Labs

Israel
On-site
Rtl implementation
Micro-architecture design
Verilog/systemverilog
Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve critical 'data bottlenecks' enabling the future of AI at scale

Job Summary

  • Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve critical 'data bottlenecks' enabling the future of AI at scale.
  • As a Senior Design Engineer, you will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware.
  • Utilize industry-leading EDA tools and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient.

Matching Summary

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve critical 'data bottlenecks' enabling the future of AI at scale.

Skills & Requirements

Must-have

  • RTL implementation
  • micro-architecture design
  • Verilog/SystemVerilog
  • high-performance hardware solutions
  • PPA targets

Nice-to-have

  • AI infrastructure connectivity
  • deep-submicron processes
  • methodology innovation
  • AI assistance tools

Key Requirements

  • 7+ years of experience in logic design
  • Bachelor's degree in Electrical Engineering
  • Experience with complex digital designs
  • Familiarity with CDC, synthesis, timing analysis

Work Rights

Not specified

Tailored Resume

Cover Letter