Job Summary

• Join the Cisco Silicon One Front-End Design Verification team, responsible for validating the most advanced networking silicon in the world.
• Develop advanced verification environments using SystemVerilog and UVM, write, run, and debug testbenches, and drive pre-silicon and in-lab debug activities.
• Collaborate with RTL, architecture, and physical design teams to achieve design closure and support methodology development, scripting, and automation.

Matching Summary

Skills & Requirements

Key Requirements

• 6+ years of experience
• Advanced knowledge of SystemVerilog and UVM
• Strong debug skills

Work Rights