Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure
Job Summary
Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.
The Senior Staff Logic Design Engineer will develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs.
Key responsibilities include RTL coding, simulation, logic optimization, design example creation, and hardware bring-up and debugging.
Matching Summary
Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.
Skills & Requirements
Must-have
RTL coding and simulation
logic design optimization
System Verilog
VCS/Synopsys simulators
Lint and Synthesis
C/C++/Perl/Python/TCL/Unix Shell script
Nice-to-have
FPGA design and programming
RTL validation
good communication skills
problem solving skills
Key Requirements
10+ years experience
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field