Senior Dft Engineer (einfochips)

eInfochips

San Jose, CA, US
Fully remote
Dft scan-insertion experience
Atpg pattern generation
Mentor tessent expertise
The role involves DFT implementation for advanced networking chips

Job Summary

  • The role involves DFT implementation for advanced networking chips.
  • Candidates will work with various tools for pattern simulation and verification.
  • Arrow offers competitive compensation and a comprehensive benefits package.

Matching Summary

The role involves DFT implementation for advanced networking chips.

Skills & Requirements

Must-have

  • DFT Scan-Insertion experience
  • ATPG pattern generation
  • Mentor Tessent expertise
  • Scripting with Perl, Shell, TCL
  • MBIST Insertion and Verification

Nice-to-have

  • Excellent communicator
  • Low power DFT experience
  • Experience with multi-million gate count SoCs

Key Requirements

  • 5-7 years of experience in DFT
  • B. Tech or M. Tech in Microelectronics/Electronics

Work Rights

Not specified

Tailored Resume

Cover Letter