Advance your career with cutting-edge verification techniques including coverage-driven verification, formal methods, and performance analysis
Job Summary
Advance your career with cutting-edge verification techniques including coverage-driven verification, formal methods, and performance analysis.
Lead custom SystemVerilog/UVM development, master industry-standard EDA tools, architect verification strategies for complex ASICs, and mentor emerging talent while independently driving verification closure.
Join our fast-paced semiconductor team where your technical leadership shapes next-generation chip development through comprehensive methodologies and innovative verification solutions.
Matching Summary
Advance your career with cutting-edge verification techniques including coverage-driven verification, formal methods, and performance analysis.
Salary
Base: CAD 153,910.00-217,280.00; Bonus/Equity: Not specified; Benefits: Not specified
Skills & Requirements
Must-have
coverage-driven verification
SystemVerilog/UVM development
industry-standard EDA tools
complex ASICs verification strategies
constrained-random testing
scripting languages (Python, TCL, Shell)
Nice-to-have
nimble, adaptable, lean, efficient
innovative and efficient methodologies
collaborative, able to communicate well
strong analytical ability
formal verification techniques and tools
Key Requirements
Bachelor's degree in STEM
5+ years ASIC/FPGA design verification
UVM and/or Formal based verification architectures
industry standard protocols (AMBA AXI/AXI-S/CHI/APB)
Low-speed communication protocols (UART, SPI or I2C/I3C)