Senior Ip Logic Design Engineer

Intel

Santa Clara, California, United States
Base: $190,610.00-269,100.00 usd annually; bonus/e...
Hybrid
10+ years in soc design
Memory coherency protocols expertise
Rtl coding in verilog or systemverilog
The role involves architecting scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs

Job Summary

  • The role involves architecting scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
  • Candidates will develop RTL code for core components of the memory fabric while ensuring optimal performance, area, and power trade-offs.
  • Intel offers a competitive total compensation package including stock bonuses, health benefits, retirement plans, and vacation time.

Matching Summary

The role involves architecting scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.

Salary

Base: $190,610.00-269,100.00 USD annually; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • 10+ years in SoC design
  • Memory coherency protocols expertise
  • RTL coding in Verilog or SystemVerilog
  • Interconnect technologies knowledge
  • Simulation tools proficiency

Nice-to-have

  • High-bandwidth memory experience
  • AI/ML accelerator background
  • Python or TCL scripting skills
  • Software-hardware co-design experience
  • Mentoring junior engineers

Key Requirements

  • MS/PhD in Electrical or Computer Engineering
  • 10+ years of SoC design experience
  • Expertise in MESI, MOESI, CXL, CCIX, or CHI protocols
  • Proficiency with EDA tools for synthesis and timing analysis

Work Rights

Not specified

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