Sr. Design Engineering Architect - Front End

Cadence

Austin, Texas, United States
10+ years front end design experience
Rtl design in verilog systemverilog vhdl
Microarchitecture definition and development
This leadership role involves guiding a team of RTL design engineers to foster a collaborative environment

Job Summary

  • This leadership role involves guiding a team of RTL design engineers to foster a collaborative environment.
  • The candidate will define microarchitectural features for IPs and subsystems while ensuring PPA goals are met.
  • Responsibilities include overseeing pre-silicon verification activities such as Lint, Clock Domain Crossing, and Formal Verification.

Matching Summary

This leadership role involves guiding a team of RTL design engineers to foster a collaborative environment.

Skills & Requirements

Must-have

  • 10+ years Front End design experience
  • RTL design in Verilog SystemVerilog VHDL
  • Microarchitecture definition and development
  • Pre-silicon verification oversight including CDC FV
  • Synthesis SDC creation and STA support

Nice-to-have

  • Experience with Cadence front end toolset
  • Self-motivated with strong communication skills
  • Proven track record in semiconductor industry

Key Requirements

  • BS/MS in Engineering or Computer Sciences
  • 10+ years of Front End design or verification
  • Rich experience in IP creation and SoC integration

Work Rights

Not specified

Tailored Resume

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