Base: $116,960 to $160,820; bonus: discretionary p...
3+ years asic/soc digital design experience
Proficiency in verilog/systemverilog
Experience with rtl-to-gds flows
The role focuses on developing and verifying RTL for digital blocks within mixed-signal SoCs for modern data centers and energy infrastructure
Job Summary
The role focuses on developing and verifying RTL for digital blocks within mixed-signal SoCs for modern data centers and energy infrastructure.
Candidates will collaborate with cross-functional teams including analog, firmware, and validation groups to integrate digital content into robust solutions.
The position offers a competitive salary range of $116,960 to $160,820 along with medical, vision, dental, and 401k benefits.
Matching Summary
The role focuses on developing and verifying RTL for digital blocks within mixed-signal SoCs for modern data centers and energy infrastructure.
Salary
Base: $116,960 to $160,820; Bonus: Discretionary performance-based bonus available; Benefits: Medical, vision, dental, 401k, paid vacation, holidays, sick time
Skills & Requirements
Must-have
3+ years ASIC/SoC digital design experience
Proficiency in Verilog/SystemVerilog
Experience with RTL-to-GDS flows
Understanding of DFT concepts and test strategies
Knowledge of analog circuit operation
Nice-to-have
FPGA prototyping and system-level modeling
Familiarity with power system components like VRMs
Exposure to AMBA, I2C, SPI protocols
Interest in methodology improvements and automation
MS degree in Electrical or Computer Engineering
Key Requirements
BS in Electrical or Computer Engineering
3+ years of experience in ASIC/SoC digital design
US Citizenship or Permanent Resident status required for export control compliance
Work Rights
Must be US Citizen, US Permanent Resident, or protected individual under 8 U.S.C. 1324b(a)(3)