Candidate will be part of the Power delivery team working on next generation Xeon Server SoC design, responsible for defining SoC level power delivery architecture and driving overall PDN convergence and Sign off
Job Summary
Candidate will be part of the Power delivery team working on next generation Xeon Server SoC design, responsible for defining SoC level power delivery architecture and driving overall PDN convergence and Sign off.
Responsibilities include block/full chip level EM/IR, PDN analysis, signal/power EM signoff, PG grid spec development, ESD analysis, and validating IR drops.
The role involves working with SOC and Packaging Teams on Bumps Assignments, RDL Enablement, and Pkg Routing optimizations to improve overall PDN Design.
Matching Summary
Candidate will be part of the Power delivery team working on next generation Xeon Server SoC design, responsible for defining SoC level power delivery architecture and driving overall PDN convergence and Sign off.
Skills & Requirements
Must-have
Block level/Full chip level EM/IR
PDN analysis
Signal EM and Power EM Signoff
PG Grid spec development
ESD analysis and Signoff
Static IR, Dynamic IR Vless, VCD Checks
Perl, TCL Scripting Skills
Nice-to-have
Good knowledge on PD
Effective cross-functional communication
Key Requirements
Bachelors (B.Tech) or Masters (M.Tech) in Electrical Engineering
8+ years of experience
Hands-on experience in PDN Signoff using Redhawk, RHSC, Voltus
Good understanding on Power Integrity Signoff Checks
Proficient in scripting languages (Tcl, Perl, Python)
Familiarity with Innovus for RDL and Bump Planning