Verification Engineer Ii

Ambarella

US Headquarters
Base: $130,000-$150,000; bonus/equity: new-hire rs...
Systemverilog and uvm methodology
Develop advanced testbenches
Debug and validate complex media processor
We are seeking a talented and motivated Verification Engineer to join our cutting-edge semiconductor development team

Job Summary

  • We are seeking a talented and motivated Verification Engineer to join our cutting-edge semiconductor development team.
  • In this role, you will be responsible for verifying complex digital logic designs, developing testbenches, and contributing to the validation of next-generation video and image processing solutions.
  • Work on industry-leading products in an innovative and collaborative environment.

Matching Summary

We are seeking a talented and motivated Verification Engineer to join our cutting-edge semiconductor development team.

Salary

Base: $130,000-$150,000; Bonus/Equity: new-hire RSU grants and annual RSU grants; Benefits: other highly competitive benefits

Skills & Requirements

Must-have

  • SystemVerilog and UVM methodology
  • develop advanced testbenches
  • debug and validate complex media processor
  • functional coverage analysis
  • drive system-level verification

Nice-to-have

  • video compression and decompression algorithms
  • memory technologies and subsystems
  • large-scale media or image processing SoCs

Key Requirements

  • Master’s degree in Electrical Engineering, Computer Engineering, or related field
  • Strong hands-on experience with SystemVerilog and UVM
  • Solid understanding of digital design concepts and SoC architecture
  • Proficiency in C/C++, scripting languages, and simulation/debug tools
  • Experience with functional and code coverage methodologies

Work Rights

Not specified

Tailored Resume

Cover Letter