Senior Verification Engineer

Altera

Jerusalem, Israel
Systemverilog/uvm
Constrained-random verification
Coverage-driven verification
Own and execute constrained-random and coverage-driven verification of high-speed SerDes mixed-signal IP

Job Summary

  • Own and execute constrained-random and coverage-driven verification of high-speed SerDes mixed-signal IP.
  • Leverage AI-assisted tools as a core part of your daily engineering workflow.
  • A collaborative and innovative environment where great ideas come from every level of the team.

Matching Summary

Own and execute constrained-random and coverage-driven verification of high-speed SerDes mixed-signal IP.

Skills & Requirements

Must-have

  • SystemVerilog/UVM
  • constrained-random verification
  • coverage-driven verification
  • Python scripting
  • digital design
  • computer architecture

Nice-to-have

  • mixed-signal IP verification
  • formal verification tools
  • high-speed protocols
  • DSP algorithm verification
  • AI-assisted engineering tools

Key Requirements

  • 4–7 years of hands-on experience
  • Bachelor's or Master's degree

Work Rights

Not specified

Tailored Resume

Cover Letter