Sr Principal Verification Engineer

Cadence

12-15 years pre-silicon asic verification experience
Formal, sv/uvm, or ovm methodology expertise
Advanced debugging with waveform viewers
The role involves applying machine learning techniques to streamline traditional pre-silicon functional verification methodologies

Job Summary

  • The role involves applying machine learning techniques to streamline traditional pre-silicon functional verification methodologies.
  • Candidates will develop agentic AI solutions using Large Language Models to accelerate the design verification process.
  • Cadence offers a collaborative culture focused on innovation, career development, and employee well-being across diverse teams.

Matching Summary

The role involves applying machine learning techniques to streamline traditional pre-silicon functional verification methodologies.

Skills & Requirements

Must-have

  • 12-15 years pre-silicon ASIC verification experience
  • Formal, SV/UVM, or OVM methodology expertise
  • Advanced debugging with waveform viewers
  • Hands-on EDA tools like Jasper, Xcelium, IMC
  • Strong programming in Verilog, SystemVerilog, Python

Nice-to-have

  • Exposure to LLMs and ML technologies
  • Experience with RAG, RFT, RL frameworks
  • Agentic AI solution development skills
  • Customer engagement and requirements gathering
  • Proactive problem-solving and continuous learning

Key Requirements

  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • 12-15 years of experience in pre-silicon verification
  • Proficiency in industry standard EDA tools

Work Rights

Not specified

Tailored Resume

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