Senior Staff Verification Engineer

Marvell Technology

Base: 139,800 - 206,900; bonus/equity: bonus + equ...
Not specified; likely hybrid based on industry standards.
Systemverilog and uvm proficiency
Develop and execute verification plans
Create and maintain testbenches
Marvell Technology is seeking a Senior Staff Verification Engineer to join its rapidly growing Custom Compute & Storage Business Unit. The ideal candidate will be responsible for functional verification of co-processor subsystems, requiring strong technical skills in SystemVerilog, UVM, and simulation tools

Job Summary

  • As a member of the verification team, the candidate will be responsible for functional verification of one or more units that make up the co-processor sub-system.
  • Develop and execute verification plans using random techniques and coverage analysis.
  • At Marvell, we offer a total compensation package with a base, bonus and equity.

Matching Summary

Match Score: 85

Marvell Technology is seeking a Senior Staff Verification Engineer to join its rapidly growing Custom Compute & Storage Business Unit. The ideal candidate will be responsible for functional verification of co-processor subsystems, requiring strong technical skills in SystemVerilog, UVM, and simulation tools.

Salary

Base: 139,800 - 206,900; Bonus/Equity: Bonus and equity included; Benefits: Health and financial wellbeing, flexible time off, 401k, year-end shutdown, floating holidays, paid time off to volunteer

Skills & Requirements

Must-have

  • SystemVerilog and UVM proficiency
  • Develop and execute verification plans
  • Create and maintain testbenches
  • Perform functional and performance verification
  • Debug and resolve design issues

Nice-to-have

  • Excellent problem-solving skills
  • Strong communication and teamwork
  • Ability to mentor junior engineers
  • Lead verification projects

Key Requirements

  • 4+ years of related professional experience
  • 3+ years of experience with Master's/PhD
  • Bachelor's degree in CS/EE or related
  • Master's/PhD in CS/EE or related
  • Proficiency in SystemVerilog and UVM
  • Experience with simulation tools
  • Knowledge of scripting languages

Work Rights

Eligible to access export-controlled information

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