Senior Analog Design Engineer

Silicon Labs

Austin, Texas, United States
Base: $124,600 - $231,400 usd annually; bonus/equi...
Hybrid
M.s. in electrical engineering or equivalent
3+ years analog/mixed-signal ic design experience
Experience with adcs, dacs, dc/dc converters, ldos
Silicon Labs is seeking an experienced engineer to develop wireless communication ICs for IoT applications within their AMS team

Job Summary

  • Silicon Labs is seeking an experienced engineer to develop wireless communication ICs for IoT applications within their AMS team.
  • The role involves designing critical analog blocks such as data converters, power management circuits, and sensors integrated into highly integrated SoCs.
  • Candidates will benefit from a comprehensive compensation package including competitive salary, equity rewards, flexible PTO, and onsite amenities like a gym and free parking.

Matching Summary

Silicon Labs is seeking an experienced engineer to develop wireless communication ICs for IoT applications within their AMS team.

Salary

Base: $124,600 - $231,400 USD annually; Bonus/Equity: Annual cash bonus and RSUs included; Benefits: Medical, dental, vision, 401k match, and flexible PTO

Skills & Requirements

Must-have

  • M.S. in Electrical Engineering or equivalent
  • 3+ years analog/mixed-signal IC design experience
  • Experience with ADCs, DACs, DC/DC converters, LDOs
  • Proficiency in schematic entry, simulation, and layout supervision
  • Knowledge of UNIX, Matlab, and circuit simulation tools

Nice-to-have

  • Experience leading other analog/mixed-signal designers
  • Low power design and implementation techniques
  • Experience with advanced technology nodes
  • Competence in behavioral modeling (VerilogA, Verilog)
  • Experience with AI-powered design tools

Key Requirements

  • M.S. in Electrical Engineering required
  • Minimum 3 years of analog/mixed-signal design experience
  • Advanced degree may reduce minimum experience requirement

Work Rights

Not specified

Tailored Resume

Cover Letter