Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure
Job Summary
Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.
In this role, you will design and develop logic design, RTL, and simulation for IP blocks, functional units, and subsystems, participating in defining architecture and microarchitecture features.
You will collaborate with SoC customers to ensure seamless integration and high-quality IP delivery, applying advanced strategies for mixed-signal designs and ensuring designs meet power, performance, area, and timing goals.
Matching Summary
Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.
Skills & Requirements
Must-have
RTL development and simulation
mixed-signal designs
high-speed connectivity
power, performance, area, and timing goals
review verification plans
customer collaboration for IP delivery
Nice-to-have
system architecture definition
digital signal processing techniques
Key Requirements
Minimum of 10 years of industry experience
Proven expertise in SerDes and PHY design
Strong background in interfacing with communication standards