Principal Product Engineer

BETA CAE Systems International AG

Shanghai, China
Ip or soc chip level design
System verilog/vhdl and hdl simulators
Uvm verification methodology
Work closely with the R&D/BU/Sales team to identify and scope opportunities for Cadence SoC Verification solution including Simulation, and SVG SW whole solution

Job Summary

  • Work closely with the R&D/BU/Sales team to identify and scope opportunities for Cadence SoC Verification solution including Simulation, and SVG SW whole solution.
  • Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
  • Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Matching Summary

Work closely with the R&D/BU/Sales team to identify and scope opportunities for Cadence SoC Verification solution including Simulation, and SVG SW whole solution.

Skills & Requirements

Must-have

  • IP or SoC chip level design
  • System Verilog/VHDL and HDL simulators
  • UVM verification methodology
  • Unix and Linux knowledge

Nice-to-have

  • customer requirement product direction
  • customer design and verification issues
  • strong teamwork skills
  • good human relationship

Key Requirements

  • Design or verification experience
  • Familiar with System Verilog/VHDL
  • UVM methodology required
  • Unix and Linux highly desired
  • Strong English communication skills

Work Rights

Not specified

Tailored Resume

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