This role offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs by leading the development of scalable STA flows and automation
Job Summary
This role offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs by leading the development of scalable STA flows and automation.
You will architect, develop, and maintain static timing analysis (STA) methodologies and flows to support full-chip and hierarchical signoff for high-speed networking ASICs.
Work with EDA vendors to drive tool evaluations, enhancements, and roadmap discussions, and drive flow standardization across business units.
Matching Summary
This role offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs by leading the development of scalable STA flows and automation.
Skills & Requirements
Must-have
Static Timing Analysis (STA) methodologies
timing closure for SoCs
SDC management and validation
automation scripts (TCL, Python)
physical implementation flows
large-scale SoC programs
Nice-to-have
networking ASIC design challenges
strong communicator and team player
version control systems
job schedulers
Key Requirements
6+ years of experience in ASIC/SoC timing analysis
Expertise in STA fundamentals
Proficiency with Synopsys PrimeTime or Cadence Tempus
Strong scripting experience in TCL, Python
First-hand experience with timing constraint (SDC) creation
Solid understanding of physical implementation flows