Base: $110,000 to $160,000 py; bonus/equity: not s...
On-site
Physical design implementation flow
Synopsys and cadence eda tools
Vlsi design expertise
Join our dynamic Test Chip Physical Implementation team in San Jose, CA, and play a critical role in bringing TSMC’s most advanced process nodes (A16/A14/A10) to life
Job Summary
Join our dynamic Test Chip Physical Implementation team in San Jose, CA, and play a critical role in bringing TSMC’s most advanced process nodes (A16/A14/A10) to life.
You will be instrumental in the physical implementation and tapeout of complex test vehicles, contributing directly to the future of high-performance computing and advanced electronics.
TSMC offers a competitive total compensation package including market competitive pay, allowances, bonuses, comprehensive benefits, and extensive development opportunities.
Matching Summary
Join our dynamic Test Chip Physical Implementation team in San Jose, CA, and play a critical role in bringing TSMC’s most advanced process nodes (A16/A14/A10) to life.
Salary
Base: $110,000 to $160,000 per year; Bonus/Equity: Not specified; Benefits: Comprehensive benefits and allowances
Skills & Requirements
Must-have
Physical design implementation flow
Synopsys and Cadence EDA tools
VLSI design expertise
Scripting in Python and TCL
Design signoff verification
Nice-to-have
Low-power design techniques
Clock tree synthesis knowledge
Power and signal integrity closure
Collaborative cross-functional teamwork
Automation script development
Key Requirements
Master’s Degree in Electrical Engineering or Computer Science
Minimum 3 years industrial experience in physical design
Experience with Synopsys ICC2, DC, Primetime, StarRC, ICV
Experience with Cadence Innovus, Virtuoso, SimVision