Asic Design & Verification Engineer

Cisco UK

Uvm based functional verification
Rtl design and micro-architecture review
Clock domain crossing (cdc) knowledge
Join the Cisco Silicon One Front-End Design team to develop the largest-scale and most advanced silicon devices

Job Summary

  • Join the Cisco Silicon One Front-End Design team to develop the largest-scale and most advanced silicon devices.
  • Engineers are responsible for reviewing micro-architecture specifications, implementing UVM-based verification environments, and resolving bugs to achieve coverage closure.
  • The role involves collaborating with firmware and lab teams to perform debug, root-cause analysis, and post-silicon validation.

Matching Summary

Join the Cisco Silicon One Front-End Design team to develop the largest-scale and most advanced silicon devices.

Skills & Requirements

Must-have

  • UVM based functional verification
  • RTL design and micro-architecture review
  • Clock Domain Crossing (CDC) knowledge

Nice-to-have

  • MATLAB simulations and bit-exact modeling
  • Mixed-signal systems experience
  • Post-silicon validation in lab

Key Requirements

  • B.Sc./M.Sc. in Electrical Engineering from a top university
  • 3+ years of experience in functional verification
  • Knowledge of UVM methodologies

Work Rights

Not specified

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