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Analog Devices is seeking an experienced Design Verification Engineer with expertise in digital SoC verification, particularly using SystemVerilog and UVM. The ideal candidate will possess strong technical skills, mentorship abilities, and a proactive approach to achieving verification goals.
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Job Summary
The role involves planning and strategizing to effectively verify both blocks and full-chip designs for a global semiconductor leader.
Candidates are expected to develop thorough verification plans using SystemVerilog, UVM, and formal verification techniques to reach verification goals.
This position requires mentoring junior engineers and supporting post-silicon verification activities in collaboration with design and applications teams.
Matching Summary
Match Score: 75
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Analog Devices is seeking an experienced Design Verification Engineer with expertise in digital SoC verification, particularly using SystemVerilog and UVM. The ideal candidate will possess strong technical skills, mentorship abilities, and a proactive approach to achieving verification goals.
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Skills & Requirements
Must-have
SystemVerilog and UVM proficiency
8-12 years digital SoC verification experience
Testplan development from ground up
Formal verification methodology knowledge
Emulation platform experience
Nice-to-have
DSP verification experience
Processor-based SoC design familiarity
Mentoring junior engineers
Python and Perl scripting skills
Post-silicon verification support
Key Requirements
B.Tech/M.Tech in EE/ECE
8-12 years of digital SoC verification experience
Proficiency in C, Perl, and Python
Strong understanding of formal verification tools
Work Rights
US Citizens, US Permanent Residents, or protected individuals preferred; others require export licensing review