Design Verification Engineer

Altera

Bengaluru, Karnataka, India
Systemverilog and uvm
Constrained-random verification environments
Directed and random test cases
You will be instrumental in ensuring the functional correctness and quality of our IP blocks for use in complex SoCs (System on a Chip)

Job Summary

  • You will be instrumental in ensuring the functional correctness and quality of our IP blocks for use in complex SoCs (System on a Chip).
  • Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
  • Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.

Matching Summary

You will be instrumental in ensuring the functional correctness and quality of our IP blocks for use in complex SoCs (System on a Chip).

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • constrained-random verification environments
  • directed and random test cases
  • verification components development
  • coverage-driven verification
  • assertion-based verification

Nice-to-have

  • industry-standard protocols
  • automation scripts and infrastructure
  • technical reviews participation

Key Requirements

  • Bachelor's or Master's degree
  • 7+ years of experience
  • ASIC or FPGA design verification
  • Verilog or VHDL
  • SystemVerilog
  • UVM-based testbenches
  • Python, Perl, or Tcl scripting

Work Rights

Not specified

Tailored Resume

Cover Letter