Senior Ip Logic Design Engineer

Intel Corporation

Santa Clara, California, US
Base: $190,610.00-269,100.00 usd; bonus/equity: st...
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Memory coherency protocols
Interconnect topologies
Rtl coding in verilog/systemverilog
** Intel Corporation is seeking a Senior IP Logic Design Engineer to develop and implement logic design and RTL coding for IP used in AI and data center SoCs. The role requires significant experience in SoC design, memory systems, and RTL coding, with a focus on performance optimization and collaboration across teams. **

Job Summary

  • Develop the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
  • Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
  • Mentor junior engineers and contribute to technical reviews and design documentation.

Matching Summary

Match Score: 75

** Intel Corporation is seeking a Senior IP Logic Design Engineer to develop and implement logic design and RTL coding for IP used in AI and data center SoCs. The role requires significant experience in SoC design, memory systems, and RTL coding, with a focus on performance optimization and collaboration across teams. **

Salary

Base: $190,610.00-269,100.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, vacation

Skills & Requirements

Must-have

  • memory coherency protocols
  • interconnect topologies
  • RTL coding in Verilog/SystemVerilog
  • performance modeling and analysis
  • physical design implications

Nice-to-have

  • emerging technologies and trends
  • software-hardware co-design
  • workflow automation

Key Requirements

  • MS/PhD in Electrical Engineering, Computer Engineering, or related field
  • 10+ years in SoC design
  • Expertise in memory coherency protocols
  • Strong knowledge of interconnect technologies
  • Proven RTL coding experience
  • Proficiency in simulation tools
  • Familiarity with physical design implications

Work Rights

Not specified

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