Fullchip Floorplan Design Engineer

Intel

Austin, Texas, United States
Base: $141,910.00-269,100.00 usd; bonus/equity: st...
Hybrid
3+ years eda tools floorplanning
1+ year synopsys fusion compiler
4+ years tcl python perl programming
The role involves top-down SoC floorplan activities including IP placement, partitioning, and pin-cutting to optimize latency and area

Job Summary

  • The role involves top-down SoC floorplan activities including IP placement, partitioning, and pin-cutting to optimize latency and area.
  • Candidates will collaborate with architects, clock design, and power delivery teams to define optimal physical dimensions and drive execution schedules.
  • Intel offers a competitive total compensation package including stock bonuses, health benefits, and a hybrid work model across multiple US locations.

Matching Summary

The role involves top-down SoC floorplan activities including IP placement, partitioning, and pin-cutting to optimize latency and area.

Salary

Base: $141,910.00-269,100.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • 3+ years EDA tools floorplanning
  • 1+ year Synopsys Fusion Compiler
  • 4+ years TCL Python Perl programming
  • 2+ years Calibre ICV verification

Nice-to-have

  • Hierarchical design approach experience
  • Large subsystem designs over 20M gates
  • Excellent communication and teamwork skills
  • Deep knowledge of thermal management

Key Requirements

  • Bachelor's degree in Engineering with 4+ years experience
  • Master's degree in Engineering with 3+ years experience
  • Experience with large subsystem designs exceeding 2GHz frequency

Work Rights

Not specified

Tailored Resume

Cover Letter