Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware
Job Summary
Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware.
Leads the Partial Reconfiguration (PR) Validation team and creates designs using HDLs and Altera IPs, verifying them for functionality and timing on Altera FPGA Hardware Boards.
Collaborates with cross-functional teams to develop and improve validation strategies for Compiler/PR validation and help resolve customer issues.
Matching Summary
Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware.
Skills & Requirements
Must-have
Partial Reconfiguration (PR) flow
Altera FPGA Hardware
Quartus Design Software
VHDL, Verilog or SystemVerilog
FPGA Partial Reconfiguration (PR) flow
HW debugging skills using SignalTap or ChipScope
Shell, Perl/TCL or Python Scripting
Nice-to-have
collaborate with cross-functional teams
resolve customer issues
improve validation strategies
Key Requirements
6+ years of relevant experience
Master's/Bachelor's Degree
FPGA Devices like Agilex, Virtex
Tools like Altera Quartus, Xilinx Vivado, Synplify
Simulation/Verification using VCS, Questa, XCelium, STA
Knowledge of AHB, AXI, PCIe, Ethernet, Avalon bus protocols