Ensure complex IP logic designs meet all functional and microarchitectural specifications by performing functional verification and developing comprehensive verification plans
Job Summary
Ensure complex IP logic designs meet all functional and microarchitectural specifications by performing functional verification and developing comprehensive verification plans.
Execute verification plans, run system simulation models, and debug issues in the presilicon environment, implementing corrective actions to resolve failing tests.
Collaborate closely with architects, RTL developers, and physical design teams, documenting test plans and contributing to technical reviews while maintaining and enhancing the verification infrastructure.
Matching Summary
Ensure complex IP logic designs meet all functional and microarchitectural specifications by performing functional verification and developing comprehensive verification plans.
Skills & Requirements
Must-have
functional verification of IP logic
develop IP verification plans
execute verification plans
debug issues in presilicon environment
Specman “e” / System Verilog language
verification methodologies
Nice-to-have
PCIe expertise is a strong advantage
collaborate closely with architects
drive quality improvements
maintain and enhance infrastructure
Key Requirements
8+ years of experience as a Verification Engineer
Solid understanding of simulation models and debugging techniques
Experience working with architecture, RTL, and physical design teams