Physical Design Engineer

Altera

San Jose, California, United States
Base: $127,400 - $184,400 usd; bonus/equity: incen...
Hands-on digital soc physical design experience
Industry-standard eda tools synopsys cadence
Scripting programming tcl python perl shell
The role involves executing critical backend implementation tasks from netlist to GDSII for FPGA and SoC devices

Job Summary

  • The role involves executing critical backend implementation tasks from netlist to GDSII for FPGA and SoC devices.
  • Candidates will collaborate with architecture, DFT, and CAD teams to achieve performance, power, and area goals.
  • The position requires developing automation frameworks using scripting languages to accelerate turnaround and improve quality of results.

Matching Summary

The role involves executing critical backend implementation tasks from netlist to GDSII for FPGA and SoC devices.

Salary

Base: $127,400 - $184,400 USD; Bonus/Equity: Incentive opportunities based on performance; Benefits: Not specified

Skills & Requirements

Must-have

  • Hands-on digital SoC physical design experience
  • Industry-standard EDA tools Synopsys Cadence
  • Scripting programming TCL Python Perl shell

Nice-to-have

  • Experience with advanced process nodes 7nm 5nm
  • FPGA architecture routing fabrics programmable logic
  • Low-power design methodologies power grid design

Key Requirements

  • Bachelor's degree in Electrical or Computer Engineering
  • 6+ years of hands-on digital SoC physical design experience
  • Expertise in high-speed digital ASIC implementation flows

Work Rights

Not specified

Tailored Resume

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