Asic Fpga Design And Verification Engineer - (experienced, Lead, Or Senior) - Mtv
The Boeing Company
Mountain View, CA, United States
Experienced (level 3): $104,550 - $141,450; lead (...
Asic/fpga design and verification
Systemverilog
Uvm test benches
Develop state-of-the-art digital ICs/SoCs to support the most critical programs across the enterprise
Job Summary
Develop state-of-the-art digital ICs/SoCs to support the most critical programs across the enterprise.
Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions.
Train and mentor less senior engineers across the department and help build effective project teams.
Matching Summary
Develop state-of-the-art digital ICs/SoCs to support the most critical programs across the enterprise.
Salary
Experienced (Level 3): $104,550 - $141,450; Lead (Level 4): $126,650 – $171,350; Senior (Level 5): $155,550 – $210,450; Benefits: Generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and paid/unpaid time away from work.
Skills & Requirements
Must-have
ASIC/FPGA design and verification
SystemVerilog
UVM test benches
Object Oriented Programming
static timing analysis
hardware integration and test
Nice-to-have
leading-edge technology
world-class partners
cross-domain applications
hardware emulators
high-speed Serdes interfaces
space-based design techniques
Key Requirements
Bachelor's degree or equivalent experience
5+ years ASIC/FPGA experience
Master's degree and 3+ years experience
Ability to obtain U.S. Security Clearance
U.S. Person for export control
Work Rights
Must have U.S. Security Clearance and be a U.S. Person