The role involves defining ISP hardware architecture based on product features and performance requirements while estimating gate count and power consumption
Job Summary
The role involves defining ISP hardware architecture based on product features and performance requirements while estimating gate count and power consumption.
Candidates will drive design activities in close collaboration with the ISP Algorithm Team to implement algorithms into hardware.
The position requires optimizing designs for reduced gate count and low power consumption using advanced verification methodologies.
Matching Summary
Match Score: 85
The role involves defining ISP hardware architecture based on product features and performance requirements while estimating gate count and power consumption.
Skills & Requirements
Must-have
ISP Algorithm implementation in HW
Verilog and SystemVerilog expertise
CMOS Image Sensor knowledge
System C/C++ programming skills
Catapult HLS tool experience
Nice-to-have
Strong debugging and problem-solving
Good communication and interpersonal skills
Adaptable to changes and results oriented
Key Requirements
Minimum MSEE or BSEE degree
3+ years of Digital Design and verification experience