Sr. Dft Engineer

NXP

Pune, India
Dft methodologies: scan, mbist, lbist, jtag
Industry standard atpg tools
Upf/cpf-based low-power dft
You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs

Job Summary

  • You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs.
  • You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.
  • You will collaborate with ATE teams for test program development and silicon bring-up while optimizing test coverage, pattern count, and test time.

Matching Summary

You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs.

Skills & Requirements

Must-have

  • DFT methodologies: Scan, MBIST, LBIST, JTAG
  • Industry standard ATPG tools
  • UPF/CPF-based low-power DFT
  • Fault models knowledge
  • Physical design constraints for DFT
  • Silicon debug and ATE bring-up

Nice-to-have

  • SoC level DFT experience
  • Exposure to high-speed interfaces
  • DFT for mixed-signal blocks
  • Strong problem-solving skills
  • Strong communication skills

Key Requirements

  • Bachelor’s or Master’s in Electrical/Electronics Engineering

Work Rights

Not specified

Tailored Resume

Cover Letter