Senior Dft Engineer

BETA CAE Systems International AG

Multiple Locations
Scan chain insertion
Memory built-in self-test (mbist)
Automatic test pattern generation (atpg)
We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT)

Job Summary

  • We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT).
  • Must be able to obtain and maintain a Department of Defense classified clearance.
  • We’re doing work that matters. Help us solve what others can’t.

Matching Summary

We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT).

Skills & Requirements

Must-have

  • scan chain insertion
  • memory built-in self-test (MBIST)
  • automatic test pattern generation (ATPG)
  • debug Verilog testbenches
  • JTAG 1149.1/6, IEEE1500 and IEEE1687

Nice-to-have

  • work in collaborative team environment
  • strong problem-solving skills
  • self-driven and committed individual
  • fast-paced project environment

Key Requirements

  • 5-15 years of professional experience
  • Department of Defense classified clearance

Work Rights

Must be able to obtain and maintain a Department of Defense classified clearance

Tailored Resume

Cover Letter