Full Chip Timing Modeling And Integration Engineer

Altera

Penang, Malaysia
Full chip timing analysis
Develop timing methodologies
Next generation fpga products
Altera is seeking highly qualified candidates to join our Full Chip Timing team to develop timing methodologies and execute full-chip timing for next generation FPGA products

Job Summary

  • Altera is seeking highly qualified candidates to join our Full Chip Timing team to develop timing methodologies and execute full-chip timing for next generation FPGA products.
  • You will work in a hands-on capacity performing full chip timing analysis, utilizing design experience to solve technical issues and communicate trade-offs with a cross-functional team.
  • Responsibilities include design understanding, interaction with front-end and back-end teams, clocking and constraints development, and debug/troubleshooting for critical design issues.

Matching Summary

Altera is seeking highly qualified candidates to join our Full Chip Timing team to develop timing methodologies and execute full-chip timing for next generation FPGA products.

Skills & Requirements

Must-have

  • Full chip timing analysis
  • Develop timing methodologies
  • Next generation FPGA products
  • Static Timing Analysis (STA)
  • Silicon modeling concepts
  • Design and Architecture understanding

Nice-to-have

  • High-performance design team
  • Efficiently solve technical issues
  • Continuous improvement
  • Negotiate technical trade-offs
  • Diverse cross-functional team

Key Requirements

  • BS/MS Degree in EE, CE, CS, or related field
  • 5+ years of relevant experience
  • Experience in SoC development
  • Experience with advanced process nodes
  • Industry standard timing formats
  • Timing modeling and library QA
  • Script writing in Python and Tcl

Work Rights

Not specified

Tailored Resume

Cover Letter