Senior Analog Layout Engineer

NXP

Multiple Locations
Custom analog layout execution
28nm, 22nm, and 16nm cmos process technologies
Cadence virtuoso layout suite proficiency
Perform full-custom analog layout for critical circuit blocks including AFEs, ADCs, DACs, PLLs, and voltage regulators

Job Summary

  • Perform full-custom analog layout for critical circuit blocks including AFEs, ADCs, DACs, PLLs, and voltage regulators.
  • Work closely with designers and cross-functional teams to ensure layouts meet foundry design rules and sign-off requirements.
  • Support silicon bring-up, debug, yield improvement, and contribute to layout guidelines and best practices.

Matching Summary

Perform full-custom analog layout for critical circuit blocks including AFEs, ADCs, DACs, PLLs, and voltage regulators.

Skills & Requirements

Must-have

  • Custom analog layout execution
  • 28nm, 22nm, and 16nm CMOS process technologies
  • Cadence Virtuoso Layout Suite proficiency
  • Calibre (DRC, LVS, PEX) expertise
  • Analog IP blocks layout experience
  • Parasitic control and noise mitigation
  • Foundry design rules compliance

Nice-to-have

  • Automotive or high-reliability semiconductor experience
  • Low-noise, high-speed analog layouts
  • Mentoring junior layout engineers
  • ISO / automotive quality flows familiarity
  • Collaboration with CAD and methodology teams

Key Requirements

  • 6–10 years custom analog/mixed-signal layout experience
  • BSEE or equivalent in Electrical/Electronics Engineering
  • Experience with advanced-node layout challenges
  • Proven work in 28nm, 22nm, or 16nm CMOS technologies

Work Rights

Not specified

Tailored Resume

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