Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, including requirements decomposition, test plan definition, coverage strategy, execution, and signoff
Job Summary
Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, including requirements decomposition, test plan definition, coverage strategy, execution, and signoff.
Collaborate cross-functionally with RTL design, architecture, DV, DFT, performance, firmware, and post-silicon validation to ensure feature completeness and testability.
Continuously improve flows by contributing to methodology, regressions, CI/CD, and verification infrastructure.
Matching Summary
Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features, including requirements decomposition, test plan definition, coverage strategy, execution, and signoff.
Skills & Requirements
Must-have
UVM/SystemVerilog testbench development
constrained-random test content
coverage closure
debug across levels
cross-functional collaboration
Python, Shell, Make/CMake scripting
Nice-to-have
problem-solving mindset
adaptability and learning agility
attention to detail
results-oriented
innovation and continuous improvement
Key Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering or related
5+ years SoC/IP design verification experience
Unrestricted, permanent right to work in Mexico
Work Rights
Must have unrestricted, permanent right to work in Mexico