Sr. Ip Logic Design Engineer

Intel

Santa Clara, California, US
Base: $190,610.00-269,100.00 usd; bonus/equity: st...
Hybrid
Memory coherency protocols
Interconnect topologies
Rtl coding verilog systemverilog
Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs

Job Summary

  • Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
  • Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks.
  • We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.

Salary

Base: $190,610.00-269,100.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • memory coherency protocols
  • interconnect topologies
  • RTL coding Verilog SystemVerilog
  • performance modeling analysis simulation tools
  • cross-functional team collaboration

Nice-to-have

  • AI/ML accelerator design
  • data center SoC design
  • scripting languages Python TCL
  • software-hardware co-design

Key Requirements

  • MS/PhD Electrical Engineering Computer Engineering
  • 10+ years SoC design experience
  • Memory systems coherency protocols RTL coding
  • Experience with EDA tools synthesis linting static timing analysis

Work Rights

Not specified

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