This role requires top-level technical leadership to define and approve digital architectures for complex mixed-signal ICs in the electrification domain
Job Summary
This role requires top-level technical leadership to define and approve digital architectures for complex mixed-signal ICs in the electrification domain.
The successful candidate will drive key architectural trade-offs across performance, power, safety, testability, and cost while mentoring digital designers.
Responsibilities include overseeing RTL design, synthesis, integration, sign-off activities, and supporting silicon bring-up and root-cause analysis.
Matching Summary
This role requires top-level technical leadership to define and approve digital architectures for complex mixed-signal ICs in the electrification domain.
Skills & Requirements
Must-have
Master's or PhD in Electrical Engineering
15+ years digital IC design experience
RTL design using SystemVerilog or Verilog
Complex multi-clock and power strategies
DFT concepts including ATPG and BIST
Automotive safety-critical design methodologies
Hands-on EDA tools like Synopsys and Cadence
Nice-to-have
Experience with BMS and gate drivers
Familiarity with Digital Signal Processing
International R&D experience
Influencing technical direction beyond single project
Key Requirements
Master's or PhD degree in Electrical Engineering
Minimum 15 years of digital IC design experience
Proven Principal or Senior Principal technical level experience